New Gate-Bias Voltage-Generating Technique With Threshold-Voltage Compensation for On-Glass Analog Circuits in LTPS Process

A new proposed gate-bias voltage-generating technique with threshold-voltage compensation for analog circuits in the low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) is proposed. The new proposed gate-bias voltage-generating circuit with threshold-voltage compensation has been successfully verified in an 8-mum LTPS process. The experimental results have shown that the impact of TFT threshold-voltage variation on the biasing circuit can be reduced from 30% to 5% under a biasing voltage of 3 V. The new proposed gate-bias voltage-generating technique with threshold-voltage compensation enables the analog circuits to be integrated and implemented by the LTPS process on glass substrate for an active matrix LCD panel.     

Ultra-High-Voltage Charge Pump Circuit in Low-Voltage Bulk CMOS Processes With Polysilicon Diodes

An on-chip ultra-high-voltage charge pump circuit realized with the polysilicon diodes in the low-voltage bulk CMOS process is proposed in this work. Because the polysilicon diodes are fully isolated from the silicon substrate, the output voltage of the charge pump circuit is not limited by the junction breakdown voltage of MOSFETs. The polysilicon diodes can be implemented in the standard CMOS processes without extra process steps. The proposed ultra-high-voltage charge pump circuit has been fabricated in a 0.25-mum 2.5-V standard CMOS process. The output voltage of the four-stage charge pump circuit with 2.5-V power-supply voltage (VDD=2.5 V) can be pumped up to 28.08 V, which is much higher than the n-well/p-substrate breakdown voltage (~18.9 V) in a 0.25-mum 2.5-V bulk CMOS process     

On-panel output buffer with offset compensation technique for data driver in LTPS technology

To overcome the offset voltage (V/sub OS/) of output buffer due to large variation on characteristics of thin-film transistor (TFT) in low-temperature polysilicon (LTPS) technology, a class-B output buffer with offset compensation circuit for the data driver is presented in this paper. This proposed class-B output buffer can operate at 50-kHz operation frequency with a 2-8-V output swing for extended graphic array (XGA) application, and it has been demonstrated in 3-/spl mu/m LTPS technology. Using the offset compensation technique, the V/sub OS/ of output buffer can be controlled within /spl plusmn/100 mV under 2-to-8 V signal operation to achieve a high resolution and quality liquid crystal display (LCD) panel.     

ESD failure mechanisms of analog I/O cells in 0.18-/spl mu/m CMOS technology

Different electrostatic discharge (ESD) protection schemes have been investigated to find the optimal ESD protection design for an analog input/output (I/O) buffer in 0.18-/spl mu/m 1.8- and 3.3-V CMOS technology. Three power-rail ESD clamp devices were used in power-rail ESD clamp circuits to compare the protection efficiency in analog I/O applications, namely: 1) gate-driven NMOS; 2) substrate-triggered field-oxide device, and 3) substrate-triggered NMOS with dummy gate. From the experimental results, the pure-diode ESD protection devices and the power-rail ESD clamp circuit with gate-driven NMOS are the suitable designs for the analog I/O buffer in the 0.18-/spl mu/m CMOS process. Each ESD failure mechanism was inspected by scanning electron microscopy photograph in all the analog I/O pins. An unexpected failure mechanism was found in the analog I/O pins with pure-diode ESD protection design under ND-mode ESD stress. The parasitic n-p-n bipolar transistor between the ESD clamp device and the guard ring structure was triggered to discharge the ESD current and cause damage under ND-mode ESD stress.     

Component-Level Measurement for Transient-Induced Latch-up in CMOS ICs Under System-Level ESD Considerations

To accurately evaluate the immunity of CMOS ICs against transient-induced latch-up (TLU) under the system-level electrostatic discharge (ESD) test for electromagnetic compatibility (EMC) regulation, an efficient component-level TLU measurement setup with bipolar (underdamped sinusoidal) trigger is developed in this paper. A current-blocking diode and a current-limiting resistance, which are generally suggested to be used in the TLU measurement setup with bipolar trigger, are investigated for their impacts to both the bipolar trigger waveforms and the TLU immunity of the device under test (DUT). All the experimental results have been successfully verified with device simulation. Finally, a TLU measurement setup without a current-blocking diode but with a small current-limiting resistance, which can accurately evaluate the TLU immunity of CMOS ICs with neither overestimation nor electrical-over-stress damage to the DUT during the TLU test, is suggested. The suggested measurement setup has been verified with silicon-controlled-rectifier test structures and real circuitry (ring oscillator) fabricated in 0.25-mum CMOS technology     

Compression and classification methods for hyperspectral images

In this article we present new lossless compression methods by combining existing methods and compare them using AVIRIS images. These methods include the Self-Organizing Map (SOM), Principal Component Analysis (PCA), and the three-dimensional Wavelet Transform combined with traditional lossless encoding methods. The two-dimensional JPEG2000 and SPIHT compression methods were applied to the eigenimages produced by the PCA. The bit allocation for the compression of eigenimages was based on the amount of information in each eigenimage. In bit rate calculation we used the exponential entropy formula, which gave better results than the original linear version. The information loss from the compression was measured by the Signal-to-Noise Ratio (SNR) and Peak-Signal-to-Noise Ratio (PSNR). To get more illustrative and practical error measures, classification of spectra was performed using unsupervised K-means clustering combined with spectral matching. Spectral matching methods include Euclidean distance, Spectral Similarity Value (SSV), and Spectral Angle Mapper (SAM). We used two test images, which both were AVIRIS images with 224 bands and 512 lines in 614 columns. The PCA in the spectral dimension combined with JPEG2000 or SPIHT in the spatial dimension was the best method in terms of the image quality and compression speed.     

Derivation of Error Distribution in Least Squares Steganalysis

This paper considers the least squares method (LSM) for estimation of the length of payload embedded by least-significant bit replacement in digital images. Errors in this estimate have already been investigated empirically, showing a slight negative bias and substantially heavy tails (extreme outliers). In this paper, (approximations for) the estimator distribution over cover images are derived: this requires analysis of the cover image assumption of the LSM algorithm and a new model for cover images which quantifies deviations from this assumption. The theory explains both the heavy tails and the negative bias in terms of cover-specific observable properties, and suggests improved detectors. It also allows the steganalyst to compute precisely, for the first time, a p-value for testing the hypothesis that a hidden payload is present. This is the first derivation of steganalysis estimator performance     

Whole-chip ESD protection design with efficient VDD-to-VSS ESDclamp circuits for submicron CMOS VLSI

A whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits is proposed to provide a real whole-chip ESD protection for submicron CMOS IC's without causing unexpected ESD damage in the internal circuits. The efficient VDD-to-VSS ESD clamp circuit has been designed to provide a low-impedance path between the VDD and VSS power lines of the IC during the ESD-stress condition, but this ESD clamp circuit is kept off when the IC is under its normal operating condition. Due to the parasitic resistance and capacitance along the VDD and VSS power lines, the ESD-protection efficiency is dependent on the pin location on a chip. Therefore, an experimental test chip has been designed and fabricated to build up a special ESD design rule for whole-chip ESD protection in a 0.8-μm CMOS technology. This whole-chip ESD protection design has been practically used to rescue a 0.8-μm CMOS IC product with a pin-to-pin HBM ESD level from the original level of 0.5 kV to become above 3 kV     

Robust Mixed Performance of Continuous Switched Systems with Time Delay

In this paper, the robust mixed H₂ / H_∞ performance analysis of switched time‐delay systems with linear fractional perturbations and distributed delay via a switching signal selection is considered. Some delay‐dependent LMI‐based criteria are proposed to achieve the design of the switching signal. Our approach is guaranteed by the new proposed inequality in recent years. Finally, some numerical examples are illustrated to show the main results.     

Preparation and application of highly porous aerogel-based bioactive materials in dentistry

In this study, the possibility of preparation and application of highly porous silica aerogel-based bioactive materials are presented. The aerogel was combined with hydroxyapatite and p.tricalcium phosphate as bioactive and osteoinductive agents. The porosity of aerogels was in themesoporous region with a maximum pore diameter of 7,4 and 12.7 nm for the composite materials. The newly developed bioactive materials were characterized by scant electron microscopy. The in vitro biological effect of these modified surfaces was also tested on SAOS-2 osteogenic sarcoma cells by confocal laser scanning microscopy.